Compilation status dock

This section describes the compilation status dock in Schematic Editor

Real-time/VHIL compilation

The compilation status window provides useful information about the compilation process state in real time, about compliation optimization, as well as about the final result. Figure 1 shows a compilation status window after a successful compilation. The information that can be found in the window are:

  1. The number of sub-circuits
  2. Model mapping to available device-specific hardware resources:
    1. Standard Processing Cores utilization
    2. MachineCores utilization
    3. UltraCores utilization
    4. Signal Generators utilization
    5. Look Up Tables utilization
  3. Model mapping to available core-specific hardware resources
    1. Power Electronics Converters utilization
    2. Contactors utilization
    3. TVE solvers utilization
    4. SP sources utilization
    5. Delayed controlled sources utilization
    6. Non-ideal switches utilization
  4. Matrix memory utilization for each SPC
  5. Simulation time slot usage for each SPC
  6. Simulation time step Ts
Figure 1. Real-time/VHIL compilation status window

TyphoonSim compilation

The compilation status window provides information about the compilation process in which we prepare model equations and simulation files so that we are able to run simulation. Any errors during compilation are also shown in the compilation status window. Figure 2 shows a compilation status window after a successful TyphoonSim compilation.

Figure 2. TyphoonSim compilation status window